1. Field of the Invention
This invention relates to a solid state imager device to which an interline transfer system is applied and which is provided with an electronic shutter mechanism.
2. Description of the Prior Art
There has conventionally been proposed an interline transfer type solid state imager device provided with an electronic shutter mechanism, the arrangement of which is schematically shown in FIG. 12.
This solid state imager device has a normal mode and an electronic shutter mode for selecting an exposure time, in a manner that the exposure time thereof can be set to one field period as well as to a predetermined time during one vertical blanking period, and comprises a solid state imager element section 1 and a timing generator 3 which is operated by a predetermined synchronizing signal supplied thereto from a synchronizing signal generating circuit 2.
The solid state imager device section 1 will first be explained in detail. On one major surface of a P-type silicon substrate 4, light recieving areas 5 each made of a photodiode are arranged in a matrix form. Vertical register sections 6 are arranged, through read-out gate areas 7, adjacent to the light receiving areas 5, to transfer charges accumulated in the light receiving areas 5 of each column of the light receiving areas 5 in the vertical direction (upward or downward direction in the sheet of FIG. 12). A horizontal register section 8 is provided on one end side of the respective register sections 6 to transfer the charges transferred downward in the sheet of FIG. 12 through the vertical register sections 6 in the horizontal direction at each horizontal line. A charge detecting section 9 are arranged at the output side of the horizontal register section 8 to detect the charges transferred through the horizontal register section 8. Thus, signals representative of images delivered from the charge detecting section 9 is derived at an output terminal 10. On the other end side of the respective vertical register sections 6, a drain region 12 is provided through discharge gate areas 11 to discharge the charges transferred upward in the sheet of FIG. 12 through the vertical register sections 6 as unnecessary charges.
As shown in FIG. 13, each of the light receiving areas 5 is constituted by a charge accumulating region 13 made of N-type region formed on the main surface of the P-type silicon substrate 4 and a insulating layer 14 made of an SiO.sub.2 layer deposited on the charge accumulating region 13. In FIG. 13, areas 15, 16 and 17 are an overflow control gate region made of P-type region, an overflow drain region made of N.sup.+ -type region, and a channel stop region made of P.sup.+ -type region, respectively. These areas are not illustrated in FIG. 12.
Each of the vertical register sections 6 as show in FIGS. 13 and 14, is formed of a charge transfer region 18 made of N-type region arranged on the main surface of the P-type silicon substrate 4 at the vicinity of the charge accumulating region 13 and transfer electrodes 19A.sub.1, 19A.sub.2, 19A.sub.3, 19A.sub.4, 19A.sub.1, . . . 19A.sub.4, each made of polycrystalline silicon deposited below the insulating layer 14 above the charge transfer region 18. The transfer electrodes 19A.sub.`, 19A.sub.2, 19A.sub.3 and 19A.sub.4 . . . are selectively supplied with four-phase phase driving pulses .phi.v1, .phi.v2, .phi.v3 and .phi.v4 for a normal-speed normal-transfer operation in which the charges are transferred toward the horizontal register section 8 at a normal speed and four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' for a high-speed inverse-transfer operation in which the charges are transferred toward the drain region 12 at a high speed. Further, a P.sup.+ -type region 20 is provided beneath the charge transfer region 18 for preventing smear.
Each of the read-out gate areas 7 arranged between each light receiving area 5 and the vertical register section 6 is formed of a read-out gate region 21 arranged between the charge accumulating region 13 and the charge transfer region 18 and a read-out gate electrode 22 deposited over the read-out gate region 21 through the insulating layer 14, as shown in FIG. 13. The read-out gate electrode 22 is formed by extending end portions of the transfer electrodes 19A.sub.1 and 19A.sub.3 of the vertical register section over the read-out gate region 21. The read-out gate electrode 22 is selectively supplied with a pulse P.sub.1 for reading out unnecessary charges and a pulse P.sub.2 for reading out signal charges, so that the charges accumulated in the charge accumulating region 13 of the light receiving area 5 can be read out to the charge transfer region 18 of the vertical register section 6.
The horizontal register section 8, a part of which is shown in FIG. 14, is formed of a charge transfer region 23 made of an N-type region arranged adjacent to the charge transfer region 18 of the vertical register section 6 and transfer electrodes 24 made of polycrystalline silicon deposited through the insulating layer 14 over the charge transfer region 23. The transfer electrodes 24 are provided so as to operate the horizontal register section 8 with two-phase driving pulses .phi..sub.H1 and .phi..sub.H2. A region 40 in FIG. 14 is a channel stop region.
The charge detecting section 9, although its detail is not illustrated, is formed of, for example, a floating diffusion amplifier.
Each of the discharge gate areas 11 is formed of a discharge gate region 25 made of an N.sup.- -type region arranged adjacent to the charge transfer region 18 of the vertical register section 6 and a discharge gate electrode 26 made of polycrystalline silicon deposited over the discharge gate region 25 through the insulating layer 14, as shown in FIG. 14. The discharge gate electrode 26 is grounded in this case.
The drain region 12 is formed of an N.sup.++ -type region 27, obtained by diffusing an N-type impurity with a high concentration into the substrate 4 adjacent to the discharge gate region 25.
The timing generator 3 is so constructed as to generate the pulse P.sub.1 for reading out unnecessary charges and the pulse P.sub.2 for reading out signal charges, which are supplied to the read-out gate areas 7, the four-phase driving pulses .phi.v1, .phi.v2, .phi.v3 and .phi.v4 of 15.77 kHz (fsc/227, where fsc=3.58 MHz) for the normal-speed normal-transfer operation and the four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' of 557 kHz (fsc/6) for the high-speed inverse-transfer operation, which are supplied to the vertical register sections 6, and the two-phase driving pulses .phi..sub.H1 and .phi..sub.H2 of 9.5 MHz which are supplied to the horizontal register section 8.
Reference is next made to the operation of the conventional solid state imager device constructed as described above.
Let it first be assumed that the normal mode is selected as the exposure time mode, wherein the exposure time period is set to one field period. As shown in FIG. 15B, the signal charge read-out pulse P.sub.2 is supplied to the read-out gates 7 at a predetermined time point during the vertical blanking period at every field, whereby the charges accumulated in the light receiving areas 5 during one field period of exposure are read out to the vertical register sections 6, as signal charges. Then, as shown in FIG. 15C, subsequent to the supply of the signal charge read-out pulse P.sub.2 to the read-out gate areas 7, the four-phase driving pulses .phi.v1, .phi.v2, .phi.v3 and .phi.v4 of 15.77 kHz for the normal-speed and normal-transfer operation are supplied through terminals 28A.sub.1, 28A.sub.2, 28A.sub.3 and 28A.sub.4 (FIG. 12) to the vertical register sections 6 to thereby transfer the read out signal charges to the horizontal register section 8. The horizontal register section 8 is being supplied with the two-phase driving pulses .phi..sub.H1 and .phi..sub.H2 of 9.5 MHz respectively through terminals 19A.sub.1 and 29A.sub.2. Thus, the charges read out as the signal charges are transferred to the charge detecting section 9 at every horizontal line, and consequently the image signals based on the signal charges are delivered to the outupt terminal 10. FIG. 15A shows the waveform of a vertical synchronizing signal V.sub.SYNC.
Next, it is assumed that the electronic shutter mode is selected as the exposure time mode, wherein the exposure time period is set to a desired time period within the vertical blanking period. As shown in FIG. 15D, at the beginning of the vertical blanking period, the unnecessary charge read-out pulse P.sub.1 is supplied to the read-out gate areas 7, whereby the charges accumulated in the light receiving areas 5 up to the vertical blanking period are read out to the vertical register sections 6 as unnecessary charges. Next, as shown in FIG. 15E, the four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' of 557 kHz for the high-speed inverse-transfer operation are supplied to the vertical register sections 6 to thereby discharge the charges read out as unnecessary charges to the drain region 12 in the course of eight horizontal periods. Next, as shown in FIG. 15D, after the desired time in the vertical blanking period has elapsed, the signal charge read-out pulse P.sub.2 is supplied to the read-out gate areas 7, in the same manner as shown in FIG. 15B to thereby read out the charges accumulated in the light receiving areas 5 after the unnecessary charge read-out pulse P.sub.1 is supplied to the read-out gate area 7 to the vertical register sections 6. Then, as shown in FIG. 15E, the four-phase driving pulses .phi.v1, .phi.v2, .phi.v3 and .phi.v4 of 15.77 kHz for the normal-speed normal-transfer operation are supplied to the vertical register sections 6, whereby the charges read out as signal charges are transferred to the horizontal register section 8. Thus, in the electronic shutter mode, the signal charges are accumulated in the light receiving areas 5 during the desired time period in the vertical blanking period, that is, from the time the unnecessary charge read-out pulse P.sub.1 is supplied to the read-out gate areas 7 to the time the signal charge read-out pulse P.sub.2 is supplied to the same, for example, for 1/1800 second, and an image signal based on those signal charges is delivered to the output terminal 10.
As described above, the solid state imager device provided with the electronic shutter mechanism does not require a mechanical shutter mechanism but can pick up an image which may rapidly move without any residual image or blurs. Therefore, when a video camera is equipped with such an imager device, the video camera can be made smaller.
However, when the above mentioned solid state imager device provided with the electronic shutter mechanism is used, a defect in image, specifically luminous or black points not related to the pick-up image, is seen on reproduced images, which does not occur with an imager device without such an electronic shutter mechanism.
The results of experiments and studies on this defect made by the inventors of the present invention show that the defect in the image is caused by potential barriers and potential dips which may exist in the charge transfer regions 18 of the vertical register sections 6.
Next, how the defect in image occurs will be explained by way of example with reference to FIGS. 16A to 16F which are potential model drawings showing potential conditions of a portion of the charge transfer region 18 of the vertical register section 6. In the drawings, solid lines 30 indicate potential levels, projections 31 potential barriers, and recesses 32 potential dips, respectively. This example shows that the potential barrier 31 and the potential dip 32 exist in the charge transfer region 18 beneath the transfer electrode 19A.sub.3 '. Particularly, it should be noted that the potential dip 32 exists at the vicinity of the charge transfer region 18 beneath the transfer electrode 19A.sub.4 '.
FIG. 16A shows that charges (unnecessary charges) 33, which are read out to the vertical register section 6 by the unnecessary charge read-out pulse P.sub.1, are transferred to the drain region 12 by the four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' for the high-speed inverse-transfer operation. This condition is next changed to the condition shown in FIG. 16B. As will be seen from FIG. 16B, a portion of the unnecessary charges 33 is trapped by the potential dip 32 and another portion thereof is accumulated on one side of the potential barrier 31 or the side of the horizontal register section 8 because of the high speed transfer. When a predetermined time, for example, eight horizontal periods, has elapsed, the unnecessary charges 33 are discharged to the drain region 12, and the supply of the four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' for the high-speed inverse-transfer operation is terminated. In this case, as shown in FIG. 16C, unnecessary charges 34 accumulated at one side of the potential barrier 31 and unnecessary charges 35, trapped in the potential dip 32, both remain.
Thereafter, the signal charge read-out pulse P.sub.2 is supplied to the read-out gate area 7 to read out to the vertical register section 6 charges accumulated in the light receiving areas 5 after the unnecessary charge read-out pulse P.sub.1 is supplied, which is shown in FIG. 16D. In this event, the unnecessary charges 34 accumulated at one side of the potential barrier 31 and the unnecessary charges 35, which are trapped in the potential dip 32, are mixed with signal charges 36. Next, the four-phase driving pulses .phi.v1, .phi.v2, .phi.v3 and .phi.v4 for the normal-speed normal-transfer operation are supplied to the vertical register section 6 to thereby transfer the signal charges 36 mixed with the unnecessary charges 34 and 35 together with adjacent signal charges 37 to the horizontal register section 8 by way of the processes shown in FIGS. 16E and 16F.
As described above, with the prior art solid state imager device provided with an electronic shutter, portions of unnecessary charges are mixed with the signal charges, and consequently the defects in image, that is, the luminous points, appear in the reproduced image.
Next, another example of such a defect in image will be explained with reference to FIGS. 17A to 17F which are potential model drawings showing potential conditions of a portion of the charge transfer region 18 of the vertical register section 6. In the drawings, solid lines 300 indicate potential levels, and recesses 320 potential dips, respectively. This example shows that the potential dip 320 exists in the charge transfer region 18 beneath the transfer electrode 19A.sub.3 ', particularly, at the vicinity of the charge transfer region 18 beneath the transfer electrode 19A.sub.2 '.
FIG. 17A shows a condition at a certain time during the process that charges (unnecessary charges) 330 read out to the vertical register section 6 by the unnecessary charge read-out pulse P.sub.1 are transferred to the drain region 12 by the four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' for the high-speed inverse-transfer operation. This condition is next changed to that as shown in FIG. 17B. As will be seen from FIG. 17A, a portion 330A of the unnecessary charges 330 is trapped by the potential dip 320. However, in the condition of FIG. 17B, the potential dip 320 is crashed by the influence of the fringing field from the transfer electrode 19A.sub.2 ', so that the unnecessary charges 320A remaining in the potential dip 320 are discharged to the charge transfer region beneath the transfer electrode 19A.sub.2 '. Therefore, the unnecessary charges 330 are all discharged to the drain region 12, and accordingly when the supply of the four-phase driving pulses .phi.v1', .phi.v2', .phi.v3' and .phi.v4' for the high-speed inverse-transfer operation has been terminated, the potential dip 320 is vacant, that is, charges are not trapped in the potential dip 320, as shown in FIG. 17C. Next, the signal charge read-out pulse P.sub.2 is supplied to the read-out gate area 7 to read out, to the vertical register section 6, charges accumulated in the light receiving areas 5, after the unnecessary charge read-out pulse P.sub.1 is supplied, as signal charges. FIG. 17D shows the condition in which the signal charges are read out to the vertical register section 6. As will be seen from FIG. 17D, a portion 360A of signal charges 360 is trapped by the potential dip 320. Then, the four-phase driving pulses .phi.v1, .phi.v2, .phi.v3 and .phi.v4 for the normal-speed normal-transfer operation are supplied to the vertical register section 6 to thereby transfer the signal charges 360 together with the subsequent signal charges 370 to the horizontal register section 8 by way of processes as shown in FIGS. 17E and 17F. Since the potential dip 320 and the transfer electrode 19A.sub.4 ' are considerably separated from each other, the potential dip 320 is not crashed by the fringing field from the transfer electrode 19A.sub.4 ', as shown in FIG. 17E. Thus, the charges 360A trapped in the potential dip 320 remain, as shown in FIG. 17F.
In the manner described above, since the portion 360A of the signal charges 360 is trapped in the potential dip 320, there is caused a defect in image, that is, black points appear in the reproduced image.